----------------------------------------------------------------------------------
-- (c) Joachim Thiemann 2010
--
-- This work is licensed under a 
-- <a rel="license" href="http://creativecommons.org/licenses/by/2.5/ca/">
-- Creative Commons Attribution 2.5 Canada License</a>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SPI_Interface is
    Port ( SS_n : in  STD_LOGIC;
           SCLK : in  STD_LOGIC;
           SI : in  STD_LOGIC;
           SO : out  STD_LOGIC;
           busy : out  STD_LOGIC;
			  valid : out STD_LOGIC;
           Tx : in  STD_LOGIC_VECTOR (7 downto 0);
           Rx : out  STD_LOGIC_VECTOR (7 downto 0));
end SPI_Interface;

architecture Behavioral of SPI_Interface is

	signal TxBuf : std_logic_vector(7 downto 0) := "00000000";
	signal RxBuf : std_logic_vector(7 downto 0) := "00000000";
	signal bitcount : std_logic_vector(2 downto 0) := "000";

begin

	Rx <= RxBuf;
	SO <= TxBuf(7);
	busy <= (SCLK and not SS_n) when bitcount="000" else '1';

	process (SCLK,SS_n)
	begin
		if SS_n = '1' then
			bitcount <= "000";
			valid <= '0';
		else
			if SCLK'event and SCLK = '1' then
				if bitcount = "000" then
					bitcount <= "111";
					TxBuf <= Tx;
				else
					bitcount <= bitcount-1;
					TxBuf(7 downto 1) <= TxBuf(6 downto 0);
				end if;
			end if;
			if SCLK'event and SCLK = '0' then
				RxBuf(7 downto 1) <= RxBuf(6 downto 0);
				RxBuf(0) <= SI;
				valid <= not bitcount(2) and not bitcount(1) and not bitcount(0);
			end if;
		end if;
	end process;

end Behavioral;