----------------------------------------------------------------------------------
-- (c) Joachim Thiemann 2010
--
-- This work is licensed under a 
-- <a rel="license" href="http://creativecommons.org/licenses/by/2.5/ca/">
-- Creative Commons Attribution 2.5 Canada License</a>.
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY SPI_Test IS
END SPI_Test;
 
ARCHITECTURE behavior OF SPI_Test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SPI_Interface
    PORT(
         SS_n : IN  std_logic;
         SCLK : IN  std_logic;
         SI : IN  std_logic;
         SO : OUT  std_logic;
         busy : OUT  std_logic;
         valid : OUT  std_logic;
         Tx : IN  std_logic_vector(7 downto 0);
         Rx : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal SS_n : std_logic := '0';
   signal SCLK : std_logic := '0';
   signal SI : std_logic := '0';
   signal Tx : std_logic_vector(7 downto 0) := (others => '0');

   --Outputs
   signal SO : std_logic;
   signal busy : std_logic;
   signal valid : std_logic;
   signal Rx : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant SCLK_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: SPI_Interface PORT MAP (
          SS_n => SS_n,
          SCLK => SCLK,
          SI => SI,
          SO => SO,
          busy => busy,
          valid => valid,
          Tx => Tx,
          Rx => Rx
        );

   -- Stimulus process
   stim_proc: process
   begin		
		SS_n <= '1';
		SCLK <= '0';
		SI <= '0';
		Tx <= "11010110";
		
      -- hold reset state for a bit.
      wait for 10us;	

		-- stimulus
		SS_n <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';

		Tx <= "00010011";
      wait for 2*SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '0';
      wait for SCLK_period;
		SCLK <= '0';
      wait for SCLK_period;
		SCLK <= '1'; SI <= '1';
      wait for SCLK_period;
		SCLK <= '0';
      wait for 2*SCLK_period;
		SS_n <= '1';
      wait;
   end process;

END;